Memory architecture exploration for programmable embedded systems

Memory Architecture Exploration for Programmable Embedded Systems addresses efficient exploration of alternative memory architectures, assisted by a "compiler-in-the-loop" that allows effective matching of the target application to the processor-memory architecture.

This new approach for memory architecture exploration replaces the traditional black-box view of the memory system and allows for aggressive co-optimization of the programmable processor together with a customized memory system.

The book concludes with a set of experiments demonstrating the utility of this exploration approach.

The authors perform architecture and compiler exploration for a set of large, real-life benchmarks, uncovering promising memory configurations from different perspectives, such as cost, performance and power.

Moreover, the authors compare the Design Space Exploration heuristic with a brute force full simulation of the design space, to verify that the heuristic successfully follows a true pareto-like curve.

Such an early exploration methodology can be used directly by design architects to quickly evaluate different design alternatives, and make confident design decisions based on quantitative figures.