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Digital design from the VLSI perspective : concepts for VLSI beginners

Variant construction from theoretical foundation to applications

Computer Architecture and Organization : Fundamentals and Architecture Security

Operational Amplifier : Theory and Experiments

Emerging computing : from devices to systems

Digital Logic Design Using Verilog : Coding and RTL Synthesis

Compact and Fast Machine Learning Accelerator for IoT Devices

Modeling and Simulation of Invasive Applications and Architectures

Invasive Tightly Coupled Processor Arrays

Quantum-Dot Cellular Automata Based Digital Logic Circuits: A Design Perspective

Quantum-Dot Cellular Automata Based Digital Logic Circuits: A Design Perspective

Invasive Computing for Mapping Parallel Programs to Many-Core Architectures

Model and Design of Improved Current Mode Logic Gates : Differential and Single-ended

Logic Synthesis and SOC Prototyping : RTL Design using VHDL

High-speed Serial Buses in Embedded Systems

Parallel Architectures, Algorithms and Programming : 11th International Symposium, PAAP 2020, Shenzhen, China, December 28–30, 2020, Proceedings

Architectural wireless networks solutions and security issues

Design Principles for Embedded Systems

Design principles for embedded systems

Proceedings of International Conference on Innovations in Software Architecture and Computational Systems : ISACS 2021

Digital design techniques and exercises : a practice book for digital logic design

A practical guide for simulation and FPGA implementation of digital design

Digital design from the VLSI perspective : concepts for VLSI beginners

Software Defined Chips : Volume II

Built-in fault-tolerant computing paradigm for resilient large-scale chip design : a self-test, self-diagnosis, and self-repair-based approach

FPGA EDA : design principles and implementation

ASIC Design and Synthesis : RTL Design Using Verilog

Software defined chipsVolume I

Parallel Architectures, Algorithms and Programming : 10th International Symposium, PAAP 2019, Guangzhou, China, December 12–14, 2019, Revised Selected Papers

ASIC design and synthesis : RTL design using Verilog

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