Writing testbenches : functional verification of HDL models (2nd ed)

The Second Edition of "Writing Testbenches, Functional Verification of HDL Models" presents the latest verification techniques to produce fully functional first silicon ASICs, systems-on-a-chip (SoC), boards and entire systems.

Topics included in the new Second Edition are: discussions on OpenVera and e; approaches for writing constrainable random stimulus generators; strategies for making testbenches self-checking; a clear blueprint of a verification process that aims for first time success; recent advances in functional verification such as coverage-driven verification process; VHDL and Verilog language semantics; the semantics are presented in new verification-oriented languages; techniques for applying stimulus and monitoring the response of a design; behavioral modeling using non-synthesizeable constructs and coding style; and, updated for Verilog 2001.