Boundary-Scan Architecture Standard IEEE-1149.1 (1990) : The Technology and Its Use

Traditional methods of testing electronic assemblies fall into two main categories - in-circuit (manufacturing defects) testing and functional testing.

For in-circuit testing, the number of circuit nodes that must be accessed is obviously high, but with the increasing complexity of digital systems, the number of access points needed for functional testing - to ensure sufficient diagnostic information to enable individual component replacement - also becomes relatively high.

Testing is also made more difficult by the diminishing sizes of PCBs, the decreasing distances between device pins, and equipment versus test equipment seed compatibility.

This report studies the boundary scan architecture standard IEEE-1149 (1990).

It is based on a single-shift register path that runs around the boundary of each IC, and it can solve many of these test problems.

After looking at the boundary-scan system architecture, the report outlines the testing philosophies for boards with boundary-scan ICs.

Available devices are listed, and some design approaches for boards, partially populated with boundary-scan ICs, are described - including ASIC and gate array devices. The current status of the systems implementation throughout the electronics industry, the companies using the system and known future developments are discussed.

The benefits and costs of implementing the system in an equipment design are evaluated, and two case studies are looked at briefly.

Some associated test issues are mentioned and useful conclusions are drawn.

Information is given on some boundary-scan products towgether with the results of a questionnaire on design for test, sent to 142 companies with electronics interest.